1. Field of the Invention
The present invention relates to an integrated circuit that emits light, an optical head that uses the integrated circuit, and an image forming apparatus that uses the optical head.
2. Description of the Related Art
FIG. 8 illustrates a conventional light emitting apparatus disclosed in Japanese Patent No. 2577089.
Referring to FIG. 8, a conventional self-scanning type light emitting apparatus includes a plurality of circuits C(−1), C(0), C(1), C(2), . . . connected in cascade, each of the plurality of circuits including a light emitting element and a transfer element.
The light emitting elements L(−1), L(0), L(1), are light emitting thyristors having a PNPN configuration.
The cathodes of the transfer elements T(−1), T(0), T(1), and the light emitting elements L(−1), L(0), L(1), . . . are connected to the ground. The gates of transfer elements T(−1), T(0), T(1), . . . and light emitting elements L(−1), L(0), L(1), . . . are connected to a power supply VGK through resistors RL.
Diodes D(−1), D(0), D(1), . . . are connected between adjacent ones of the plurality of circuits. The cathodes of the diodes are connected to the gates of transfer elements and the gate electrodes of the light emitting elements of a preceding one of adjacent circuits. The anodes of the diodes D(−1), D(0), D(1), . . . are connected to the gates of transfer elements and the gate electrodes of the light emitting elements of a following one of the adjacent circuits.
The anodes of the transfer elements T(−1), T(1), . . . are connected to a φ2 terminal. The anodes of the transfer elements T(0), T(2), . . . are connected to a φ1 terminal. Clock signals are fed to the φ1 terminal and the φ2 terminal, and a write signal Sin is fed to a Sin terminal to control light emission of the light emitting elements L(−1), L(0), L(1), . . . .
The anodes of the light emitting elements L(−1), L(0), L(1), . . . are connected to the Sin terminal.
Such a light emitting apparatus is configured such that the transfer elements T(−1), T(0), T(1), . . . and the light emitting elements L(−1), L(0), L(1), . . . are separately implemented, and that the write signal Sin is fed to the light emitting elements L(−1), L(0), L(1), . . . via the Sin terminal. Therefore, the circuit configuration of the light emitting apparatus can be apparently simplified.
Assume that the transfer element T(0) is in the ON state, the gate electrode of the transfer element (T(0) is nearly at zero volts, lower than the supply VGK (e.g., 5 V). The write signal Sin higher than the diffusion voltage of a pn junction (approximately 1 V) of the light emitting element L(0) is high enough to cause the light emitting element L(0) to turn on.
At this moment, the transfer element T(−1) is in the OFF state. The potential of the gate electrode of the transfer element T (−1) is approximately equal to VGK so that the diode D(1) is reverse-biased to allow some charges on the gate of the transfer element (T(−1) to flow into the gate of the transfer element T(1).
At this moment, the transfer element T(1) is also in the OFF state. Thus, the diode D(0) is forward-biased through the resistor RL in the circuit C(1), so that the potential of the gate of the transfer element T(1) is substantially equal to the forward voltage of the diode D(0) (e.g., approximately 1 V).
Thus, the voltage of the write signal Sin required for turning on the light emitting element L(1) is about 2 V, which is the sum of the forward voltage of the diode D(0) and the diffusion voltage of the pn junction of the light emitting element L(1). Thus, the voltage of write signal Sin required for turning on the light emitting element L(−1) is approximately 6 V.
In other words, the voltages of the clocks φ1 and φ2 for driving the transfer elements T(−1), T(0), T(1), . . . should be in the rage of 1 to 2 V. If the voltage of the clock φ2 exceeds 1 to 2 V (e.g., 3 V) momentarily due to noise, the momentarily increased voltage is applied to the anode electrode of the transfer element T(1) and is fed to the diodes D(1) and D(0) through the gate of the transfer element T(1), thereby creating a current path of D(0)→D(−1)→T(−1)→ground. In other words, a small amount of noise in the signal supplied from the φ1 terminal or the φ2 terminal causes the transfer elements T(−1), T(0), T(1), . . . to malfunction. In addition, the write signal Sin should be in a narrow voltage range in order to ensure the normal operation of the light emitting apparatus.